The present invention relates to a semiconductor integrated circuit and a method for designing the semiconductor integrated circuit. Especially, when the semiconductor integrated circuit is on a system provided from a user (referred to as “user system”) and needs to autonomously perform a self diagnosis, the semiconductor integrated circuit is suitably usable.
A standard method of boundary scan testing, which is one of the verification methods of semiconductor integrated circuits, is an IEEE standard 1149.1 (hereinafter, referred to as “JTAG”). A JTAG-compliant semiconductor integrated circuit includes, in addition to circuitry that performs originally intended functions, JTAG-compliant circuitry, and signal (TCK, TRST, TMS, TDI, TDO) pins corresponding to a test access port (TAP) of a JTAG interface.
One of the techniques of design for testability (DFT) for semiconductor integrated circuits is built-in self-testing (BIST). BIST is implemented with circuitry that generates test patterns and circuitry that compares test results and the expectations. BIST designed for memory is called “MBIST”, and BIST designed for logic circuitry is called “LBIST”.
Japanese Unexamined Patent Application Publication No. 2003-208331 discloses a method and a device for executing a memory built-in self-test and a logic built-in self-test on an integrated circuit device. According to the disclosure, a dual mode BIST controller includes a LBIST engine and a MBIST engine and executes at least one of the engines to obtain test results therefrom.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2004-505395 discloses a technique of providing system initialization of microcode-based MBIST. In this disclosure, an integrated circuit with an embedded memory and a BIST architecture includes means for generating self-diagnostic test instructions.